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dsPIC33CH Dual-Core DSPs

Release on : Jun 28, 2018

Microchip Technology's innovative dsPIC33CH dual-core DSPs have two dsPIC® cores in a single chip that provides easy software integration for system developers designing high-end embedded control applications with multiple software teams. The dsPIC33CH has one core that is a master while the other is a slave. The slave core is for executing dedicated, time-critical control code. The master core runs the user interface, system monitoring and communications functions, and customizations for the end application. The dsPIC33CH is designed to facilitate independent code development for each core by separate design teams and later enables seamless integration when they are brought together in one chip. The dsPIC33CH family is optimized for high-performance digital power, motor control, and other applications requiring sophisticated algorithms. This includes applications such as wireless power, server power supplies, drones, and automotive sensors. The dsPIC33CH is supported by Microchip’s MPLAB® development ecosystem including MPLAB X integrated development environment (IDE). Supported by the popular MPLAB code configurator (MCC) tool, setting up pin assignments, peripheral modes, and application stacks has never been easier, drastically reducing customers’ design cycles and time-to-market.

  • Simplified firmware development with dual independent cores
  • Dual cores and peripheral sets facilitate robust systems and improve functional safety
  • First dsPIC33 with CAN-FD for robust communication with increased bandwidth
  • Digital power
    • Industrial: AC/DC and DC/DC power supplies
    • Automotive: converters, chargers, and inverters
    • Consumer: wireless power
  • Motor control
    • Automotive: pumps and fans
    • Industrial: drones and robotics
    • Consumer: appliances and toys
  • High-performance embedded
    • Automotive: electronic sensors
    • Industrial: automation and control
    • Medical: diagnostic equipment, and monitors
    • IoT: gateways and central processors